Method and apparatus for CDMA code domain parameter estimation

ABSTRACT

The testing and verification of CDMA cellular base stations requires a number of parameters to be measured. Many of these parameters are measured in the code domain where individual waveforms are extracted from a composite waveform through the use of orthogonal codes. A method and apparatus is described for measuring many code domain parameters using a modified code domain power measurement technique. The apparatus is comprised of a chip timing recovery circuit (46), a reference generator (78), a multiplier (60), various summers and absolute value operations, a memory (76), and a processor (90). In addition, a reference generator (78) for generating an improved reference waveform is described. Reference generator (78) is comprised of a Walsh code generator (200), an I channel PN sequence generator (202), a Q channel PN sequence generator (204), an XOR gate (206), and an XOR gate (208). This improved reference waveform allows for greater code domain parameter measurement accuracy without requiring tighter input frequency tolerances.

TECHNICAL FIELD

This invention relates generally to digital cellular communicationssystems and, in particular, to methods and systems for the testing ofCDMA cellular base station telephone equipment.

BACKGROUND OF THE INVENTION

Cellular communications have become widespread in recent years. Asspread-spectrum code division multiple access (CDMA) systems become moreprevalent in today's cellular systems, a need has arisen to provide testequipment for the CDMA cellular base station telephone equipment.

The testing of CDMA base station telephone equipment is specified in theTelecommunication Industry Association (TIA) Interim Standard 97(IS-97). Among the tests specified by IS-97 are a class of parametersdesigned to measure what is hereinafter referred to as the CDMA basestation "waveform quality." These waveform quality parameters provide acharacterization of the code domain channels of a CDMA base stationtransmitter. One measurement, code domain power, is used to measure thedistribution of power among code channels. Other measurements such ascode domain timing and code domain phase, reflect timing and phaseerrors of code channels relative to the pilot channel. Thesemeasurements are important because subscriber units make allmeasurements of code channels based on timing and phase of the receivedpilot channel. IS-97 provides for maximum offsets in phase and timing toguarantee that subscriber units will function satisfactorily.

Within IS-97, it is suggested that the waveform quality parameters bemeasured using certain computationally complex algorithms. Specifically,IS-97 suggests that a large number of simultaneous equations be solvedcontinuously during the measurement process. The continuous solving of alarge number of simultaneous equations is costly in terms processingpower and time. It is desirable, therefore, to reduce or eliminate theneed for simultaneous equation solving, thereby reducing the hardwareand time required to perform the measurements.

Further, it is recognized in the art that measurement accuracy can besubstantially increased by increasing the length of a correlation in thesuggested algorithm as presented in IS-97. It is also well recognized inthe art that as the correlation length is increased, the frequencyoffset of the input signal must be controlled more tightly to minimizethe phase rotation during any one correlation time. It is desirable,therefore, to be able to increase measurement accuracy by increasing thecorrelation time without necessitating tighter input frequency control.

Hence, there exists a need for an apparatus and method for measuringCDMA base station waveform quality parameters which is bothcomputationally simpler and faster than current approaches as known inthe art.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is pointed out with particularity in the appended claims.However, other features of the invention will become more apparent andthe invention will be best understood by referring to the followingdetailed description in conjunction with the accompanying drawings inwhich:

FIG. 1 shows an overview diagram of a system for CDMA code domainparameter estimation in accordance with the present invention.

FIG. 2 shows a diagram of a reference signal generator in accordancewith one aspect of the present invention.

FIG. 3 shows a flow diagram illustrating the steps necessary beforemeasuring code domain parameters in accordance with one aspect of thepresent invention.

FIG. 4 shows a flow diagram of a method for determining frequency offsetin accordance with one aspect of the present invention.

FIG. 5 shows a flow diagram of a method for determining fine timing fora code channel in accordance with one aspect of the present invention.

FIG. 6 shows a flow diagram of a method for determining the timing of acode channel relative to that of the pilot channel in accordance withone aspect of the present invention.

FIG. 7 shows a flow diagram of a method for determining the phase of acode channel relative to that of the pilot channel in accordance withone aspect of the present invention.

FIG. 8 shows two probability density functions that result from asummation in accordance with one aspect of the present invention.

FIG. 9 shows a circuit used to reduce errors while increasing accuracyin accordance with one aspect of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

As mentioned earlier, the testing of CDMA base station equipment isspecified in the industry standard TIA-IS-97. TIA-IS-97 is incorporatedby reference herein.

Specifically, IS-97 specifies the following equation for the measurementof code domain power: ##EQU1##

The code domain power equation as shown above represents the power in anindividual CDMA channel divided by the total power measured at thesampling time. When i=0, the equation measures ρ_(o) or the power in thepilot channel. For i=1 to 63, the power equation measures ρ_(i), thecode domain power for the i-th Walsh channel. The numerator includes theterm Z, which represents a sampled version of the composite CDMAwaveform at baseband, and R*, which represents the complex conjugate ofa reference waveform that is made up of the Walsh code, and the shortPseudo Noise (PN) code. Z and R* are correlated together over the Walshperiod of 64 chips. The resulting summation is squared which then yieldspower for a given i-th CDMA channel. That power value is then summedover a plurality of Walsh periods. IS-97 specifies a minimum of 20 suchperiods, and the preferred embodiment described herein uses a value of256, but it will be readily apparent to one skilled in the art that anyvalue could be substituted while still practicing the present invention.

The denominator of the code domain power equation, which represents thetotal power measured at the sampling time, includes the power of theincoming composite CDMA waveform, Z, summed over the 64 chips of asingle Walsh period and then summed over the same number of Walshperiods as used in the numerator. Also in the denominator is the powerof the reference waveform summed over the 64 chips in a single Walshperiod.

It should be noted that the code domain power equation assumes thatproper timing has been established. For Z and R* to correlate correctlyin the numerator of the equation, the short code as used in thereference generator must match the short code and offset as present inthe incoming composite waveform. In addition to the short code, theWalsh code must be aligned at a period boundary. In addition to thiscoarse timing of codes, the sample timing within a chip interval mustalso be correct.

The present invention recognizes that the hardware that determines thenumerator of the code domain power equation can also be utilized tocalculate Δf_(o), τ_(o), φ_(o), Δτ_(i), and Δφ_(i), as will be definedand discussed shortly. The measurement techniques practiced in thepresent invention take advantage of the complex correlation as presentin the numerator of the code domain power equation.

Δf_(o) is the frequency error of the composite CDMA signal. Bydefinition all code domain channels, including the pilot, are at thesame carrier frequency. Δf_(o) can be determined by taking the phasedifference of the pilot channel at two different times. The phase of achannel is calculated as discussed in detail below.

τf_(o) is the pilot timing relative to the 2 second CDMA base stationtiming reference. The coarse timing, more than 1 chip time, isdetermined by looking at the correlation between the reference (R*) andcomposite CDMA input signal (Z). The reference signal is time shifted 1chip at a time until the correlation process indicates that thereference and composite input signal are timed within 1 chip period.Once the coarse timing is determined within 1 chip time, fine timing,for example, 1/64_(th) chip, is established between the composite inputsignal and the reference signal shifted by ±1/2 chip time. Thistechnique is well established in literature and is often referred to as"early-late gate". It will be shown that the coarse and fine timingalgorithms use the Z·R* correlation function as found in the numeratorof the code domain power equation.

Δτ_(i) is the Walsh code domain time offset relative to the pilot forthe i-th code channel. Δτ_(i) is defined as τ_(i) -τ_(o). The timingoffset of τ_(i) is calculated identically to τ_(o) except that thecorrelation reference signal is the i-th channel, where i is between 1and 63, rather than the 0-th, or pilot channel.

Δφ_(i) is the Walsh code domain phase offset of the i-th channelrelative to the 0-th, or pilot channel. Δφ_(i) is defined as φ_(i)-φ_(o). The present invention recognizes that an important aspect todetermining φ_(o) or φ_(i) is to recognize that the phase between twocomplex pseudo-random codes can be determined by correlating the twocomplex signals. In the case at hand, one of the pseudo-random signalsis that of the i-th channel code, while the other signal is that of thecomposite CDMA signal.

The present invention further simplifies the task of measuring thewaveform quality parameters by greatly simplifying the generation of therequired reference waveform. One known method for generating a referencesignal is to use a closed loop system wherein a search procedure whichminimizes the mean square difference between the base band test signaland a synthesized reference signal is performed. This generally requiresa two step process wherein the data contained in Z is demodulated andthen the reference signal R is constructed. After R is constructed, alarge number of simultaneous equations is solved to minimize the errorbetween Z and R. This method is costly and time consuming. The presentinvention recognizes that this complex method of generating a referencesignal is not necessary. The present invention implements a methodwhereby the data in the input waveform Z is not needed, so that thedemodulating step is obviated. Further, the present invention implementsa method whereby the reference R consists solely of positive andnegative 1's thereby simplifying the complex multiplications, Z·R*.

Other approaches to measuring code domain parameters require thesynthesizing of this rather complex reference signal because theresultant timing and phase of the synthesized reference relates directlyto the measurements to be made. Because the present invention measuresall of the code domain parameters using a variation of the code domainpower equation, the need for synthesizing the complex reference isobviated. There are other advantages to using this simplified referenceas will be explained below in conjunction with the drawings.

Now, referring to FIG. 1, there is shown a system for the estimation ofCDMA code domain parameters, generally designated by reference number10. An A/D 30 is shown receiving an incoming composite CDMA signal at anintermediate frequency (IF). The start of the analog to digitalconversion process is triggered by the two second timing reference putout by the base station. A/D 30 outputs digitized IF samples which areinputs to quadrature down converter 40. Quadrature down converter 40uses techniques well-known in the art to bring the digitized IF samplesdown to baseband samples represented by I and Q. Baseband samples I andQ are input to baseband complementary nyquist filters 42. Nyquistfiltering is also well-known in the art. I and Q samples output from thebaseband complementary nyquist filters 42 are then stored in memory 44.

The foregoing discussion describes a method for converting a compositeCDMA signal at an intermediate frequency to a digitized, down converted,and filtered version. There are many ways to accomplish the same task,and those skilled in the art will recognize that any of many alternatearchitectures could be used for the conversion while still practicingthe present invention.

Memory 44, then, has as contents a burst of samples which start at thetwo second trigger event and continue in time for a number of samples.Any size memory can be used for memory 44; a larger memory allows formore time data to be stored. The A/D clock and the clocks running thequadrature down converter 40 and baseband complementary nyquist filters42 are such that the digitized information stored in memory 44 iscomprised of two complex samples per chip. It will be readily apparentto one skilled in the art that more or less than two complex samples perchip could be substituted. Once memory 44 has acquired a frame ofbaseband I and Q data at two complex samples per chip, the acquisitionprocess can be considered complete. Memory 44 is configured such thatthe contents representing I and Q baseband samples at two complexsamples per chip can be repeatedly output to stimulate the remainingblocks shown in FIG. 1 an indeterminate number of times. This allows fora number of measurements to be made very rapidly with a single set ofacquired data.

Memory 44 has, as an input, a coarse timing control word. This coarsetiming control word serves as an offset into the memory so that adifferent portion of the memory's contents will stimulate the remainingblocks. By modifying the coarse timing control word, the short code andthe Walsh code can be time aligned with that of the reference generator.

The coarse timing control word is shown in FIG. 1 as being provided byprocessor 90. Other control words are shown in FIG. 1 as being suppliedby processor 90, and memories are shown as being accessible by processor90. Processor 90 represents a processor means well known in the art, andcould conceivably be comprised of a DSP, microcontroller, generalpurpose processor, or the like. Processor 90 could also be comprised ofdedicated hardware, thereby increasing the speed. The particulars ofthis processor are not important to the present invention.

When I and Q baseband samples at two complex samples per chip are outputfrom memory 44, they are input to chip timing recovery circuit 46. Thefunction of the chip timing recovery circuit 46 is to interpolate and toprovide one of 64 possible values within a chip period. Because all 64intra-chip samples are not required at the output of chip timingrecovery circuit 46, the chip timing recovery circuit 46 may includedual 8 tap FIR filters, which are single legs of a 256 tap polyphase FIRfilter. The output of chip timing recovery circuit 46 is one complexbaseband sample per chip, properly timed. The selection of the correctFIR filter coefficients which reside within the chip timing recoverycircuit 46 is accomplished via the fine timing control informationprovided to chip timing recovery circuit 46. It will be recognized byone skilled in the art that through manipulation of fine timing controlinput to chip timing recovery circuit 46, different intra-chip timingvalues can be presented at the output of chip timing recovery circuit46. Of course, there are other methods available to interpolate andrecover intra-chip values, including methods that would generate anarbitrarily large number of possible values within a chip. Those methodsare intended to be included within the scope of the present invention.

The I and Q outputs from the chip timing recovery circuit 46 are theninput as a multiplicand to complex multiplier 60. Complex multiplier 60also has as a multiplicand the output of reference generator 78. Theoutput of reference generator 78 is the I and Q representation of theideal reference after going through the cascaded transmit andcomplementary receiver filters which should give zero intersymbolinterference (ISI) at the decision point. The present inventionrecognizes that if samples are taken at the correct time, so that theintra-chip samples are timed correctly, then the reference generator 78output need only consist of positive 1's and negative 1's. Whenreference generator 78 has output consisting solely of positive andnegative 1's, multiplier 60 becomes a much simpler block as will beexplained later. Output of reference generator 78 is represented by R*in the numerator and denominator of the code domain power equation.Reference generator 78 is shown in more detail in FIG. 2.

Referring now to FIG. 2, the internals of reference generator 78 areshown. Reference generator 78 has as inputs the Walsh code value, i,which specifies which of 64 possible Walsh codes are to be used in thegeneration of the reference, and a PN offset value which specifies anoffset into the short code. Walsh code generator 200 outputs the Walshcode as specified by the Walsh code value and the Walsh code is theninput to exclusive-OR (XOR) gates 206 and 208. I channel PN sequencegenerator 202 receives the PN offset value and generates a PN code forthe I channel and outputs it to XOR gate 206 where the PN code for the Ichannel is combined with the Walsh code to produce the I channelreference signal which is a part of the reference generator 78 output. Qchannel PN sequence generator 204 takes PN offset as input and generatesa PN sequence corresponding to the Q channel and outputs that to XORgate 208 which then combines the Q PN sequence with the Walsh code togenerate the Q channel reference signal which is a part of referencegenerator 78 output. The PN offset is used to distinguish from one basestation to the next. There are 512 possible offset values into the shortcode, allowing 512 base stations to be orthogonal to each other. TheWalsh code has 64 possible values and serves to provide orthogonalitybetween users of the same base station.

From the discussion in the previous paragraph, it can be seen that thereference generator of the present invention is substantially simplerthan any reference generator capable of generating a reference signalusing a minimized sum-squared-error technique. One advantageous aspectof the reference generator of the present invention is that it requiresno knowledge of the data in the CDMA waveform being measured. Thisreference which contains no data is termed a dataless reference and thereference generator which generates this reference is termed a datalessreference generator. The dataless reference generator of the presentinvention is advantageous because the implementation is smaller, faster,and consumes less power than other known approaches.

Referring back to FIG. 1, the output of reference generator 78 is amultiplicand for multiplier 60. Because reference values output fromreference generator 78 consist solely of positive 1's and negative 1'swhich can be represented by binary values, multiplier 60 is reduced to aconditional negation operation. One skilled in the art will recognizethat this simplification is of great benefit in a hardwareimplementation.

The output of multiplier 60, then, is Z multiplied by R which forms thebasis for the numerator of the code domain power equation. As shown inthe code domain power equation, the product of Z and R* is summed over64 chips of a Walsh code which constitutes a single Walsh code period.Block 64 in FIG. 1 shows a summing operation which performs thissummation of the Z and R* product over, and bounded by, a single Walshperiod. This summation operation must be bounded at the Walsh periodboundaries or interference from adjacent CDMA channels will occur. Theoutput of block 64 then, is that portion of the numerator of the codedomain power equation that exists between absolute value signs. Theoutput of summer 64, still represented by I and Q values, is input toblock 68 which performs an absolute value and squaring operation. Theoutput of block 68 then, represents that portion of the numerator of thecode domain power equation that is squared. The output of block 68 isinput to block 72. Block 72 functions as the summer which sums over N inthe numerator of the code domain power equation. IS-97 specifies that Nhave a minimum value of 20, but in the preferred embodiment of thepresent invention being set forth the value of N is 256.

The output of block 72 represents the entire numerator of the codedomain power equation. This numerator value is output from block 72 andinput to memory 76. Memory 76 is a conventional random access memorywhich can be accessed by processor 90. Memory 76 also has as inputsother values that will now be discussed.

The output of chip timing recovery circuit 46, which represents Z, isinput to block 62 where it is squared. The output of squaring block 62is then input to summer block 66, where a summation is performed over,and on the boundaries of, the same Walsh period that was summed over inblock 64. The output of block 66 is then input to summer block 74 whichsums over a plurality of Walsh periods and is controlled in a likemanner to that of summer block 72. Again, in the preferred embodimentbeing set forth the sum is performed over 256 Walsh periods. The outputof block 74 represents that portion of the denominator of the codedomain power equation which is a function of Z. The remainder of thedenominator of the code domain power equation, which is a functionstrictly of R, is reduced to a known constant because R, the output ofreference generator 78 consists of positive 1's and negative 1's, whichwhen squared yield the value of 1. This simplification of thedenominator as a result of the reference generator design provides asignificant savings in hardware required to perform the waveform qualityparameter measurements.

The output of block 64, which represents the correlation of Z and R*over 64 chip periods, is input to summer 70, which is identical infunction to summers 72 and 74. Summer 70 can sum over any number ofWalsh integrations but in the preferred embodiment being set forth,summer 70 sums over 256 Walsh periods. The output of block 70 is theninput to memory 76 for later retrieval by processor 90.

The present invention recognizes that the output of block 64 can beinterpreted in polar coordinates as represented by a magnitude and aphase. The present invention further recognizes that when summed over aplurality of Walsh periods as summer 70 performs, the phase measurementcan be made more accurate. It is this accurate phase measurement outputby block 70 and input to memory 76 that is used in the determination ofthe waveform quality parameters, as will be described in detailhereinafter.

The contents of memory 76 as read by processor 90 are used in thecalculation of the waveform quality parameters. The numerator and thenon-constant portion of the denominator of the code domain powerequation reside in memory 76. In addition, an accurate phase valuecorresponding to the phase of Z as output from chip timing recoverycircuit 46 is stored in memory 76. The values of these intermediatevariables stored in memory 76 reflect the effects of the coarse timingcontrol word which is input to memory 44, the fine timing control whichis input to chip timing recovery circuit 46, the Walsh channel selectionand PN offset selection which are both input to reference generator 78,and the number of Walsh integrations input to summers 70, 72, and 74.

Referring now to FIG. 3, a flowchart is shown that illustrates therequired sequence of events to achieve proper timing before measuringwaveform quality parameters. The steps in FIG. 3 assume that memory 44has baseband I and Q samples stored at two samples per chip. Further,FIG. 3 assumes that memory 44 has the ability to output the I and Qbaseband samples an indeterminate number of times. Step 300 has as itspurpose to adjust the coarse timing. The coarse timing of more than onechip time is determined by looking at the correlation between thereference and composite CDMA input signal. The reference signal is timeshifted one chip at a time until the correlation process indicates thatthe reference and composite input signal are timed within one chipperiod. This correlation value corresponds to the ratio of the numeratorand the denominator of the code domain power equation as stored inmemory 76. After step 300 is complete, step 302 is performed whichmeasures the frequency offset of the input composite CDMA signal. In thepreferred embodiment of the present invention, it is necessary to havefrequency offset of less than or equal to 200 Hz in order to meet themeasurement accuracy as specified in IS-97. Step 302 measuring frequencyoffset, is shown in more detail in FIG. 4.

FIG. 4 shows the calculation of the frequency offset and illustrates howthe accurate phase value as output from block 70 and stored in memory 76is utilized. Because the present invention is capable of utilizing theinformation stored in memory 44 multiple times, phase measurements canbe made more than once and at different points in the sample sequencethat represent different points in time, resulting in two distinct phasevalues which, when subtracted, yield frequency offset. Step 400corresponds to the first phase measurement at the first time in thesample sequence. The product of Z and R* is integrated over a pluralityof Walsh periods. After the integration in step 400 the first phasevalue is stored in memory 76 in step 402. Then, in step 404, a secondintegration of the product of Z and R* is performed over a sequence ofsamples that represent a later point in time. Then, in step 408, thesecond phase value is stored in memory 76. Now, having both first andsecond phase values stored in memory 76, and having informationregarding the time difference of the two phase measurements, processor90 can determine frequency offset by taking the difference between thetwo values as shown in step 410.

Referring back to FIG. 3, if the frequency offset as found in step 302is greater than or equal to 200 Hz, then this frequency offset will beremoved in step 304. Processor 90 can remove the frequency offset fromsamples contained in memory 44 using well-known techniques. Processor 90can multiply the sample stream contained in memory 44 by a complexrotating phasor that represents the frequency offset to be removed. Ofcourse, other conventional techniques for frequency removal arecontemplated, such as an additional complex LO and multiplierimplemented in hardware (not shown). In general, frequency translationtechniques for use with complex samples are well known in the art. Afterthe frequency offset has been removed in step 304, the fine timing isadjusted in step 306. Step 306 is shown more fully in FIG. 5.

Referring now to FIG. 5, a flow diagram illustrating the steps used inthe fine timing determination is shown. Steps 500 and 502 compute codedomain power at plus 1/2 chip and minus 1/2 chip, respectively. Step 504subtracts the code domain power measured at plus 1/2 chip from thecode-domain power measured at minus 1/2 chip to yield a powerdifference. This calculation takes advantage of the fact that if thesamples are properly timed the power at plus 1/2 chip and the power atminus 1/2 chip will be equal. If the power values are not equal then atiming modification may possibly be made. In step 506 the powerdifference is compared to a threshold. If the power difference isgreater than a threshold, indicating a timing offset that is too large,fine timing is adjusted in step 508. The fine timing is adjusted bymodifying the fine timing control which is an input to chip timingrecovery circuit 46. As shown in FIG. 5, the timing adjustment is aniterative process and continues until the power difference is less thanthe threshold. Once the power difference found is less than thethreshold, the fine timing has been found. It should be noted that thealgorithm shown in FIG. 5 is valid for acquiring timing of any channelincluding channel 0 (pilot channel) and channels 1-63 (code channels).After fine timing is adjusted in step 306 the parameters can be measuredin step 308. The timing found in step 306 when i is equal to 0 is thepilot timing offset, τ₀, which is measured relative to the two secondreference timing reference put out by the base station.

FIG. 6 shows the method used for measuring the timing of the 63non-pilot channels relative to the pilot channel, Δτ_(i). Step 600calculates fine timing for the pilot channel, τ₀, which is equivalent toexecuting the steps in FIG. 5 with i=0. Step 602 comprises the step ofdetermining the fine timing of CDMA channel i, τ_(i), which isequivalent to the algorithm in FIG. 5 with i equal to the channel ofinterest. Step 604 shows the calculation of the timing of CDMA channel irelative to the pilot channel which is the difference between theprevious two measurements. The timing of all 63 non-pilot channelsrelative to the pilot channel are measured in this manner.

FIG. 7 shows the method used to measure the phase of the 63 non-pilotchannels with respect to the pilot channel, Δφ_(i). All measurementsshown in FIG. 7 are performed with sample timing as found with the pilotchannel. In step 700 the correlation of the reference and the compositeinput signal are integrated over a plurality of Walsh periods for thepilot channel. In step 702, the resulting pilot channel phase value φ₀is stored in memory 76. In step 704, the correlation of the referencesignal R* with the composite input signal Z for channel i are integratedover the same set of Walsh periods. In step 706, the resulting phasevalue for channel i, φ_(i) is stored in memory 76. The phase differenceis then calculated in step 708 as the difference between the phase ofchannel i and the phase of the pilot channel. The method of FIG. 7 isrepeated 63 times for the measurement of the 63 non-pilot channels.

The numerator of the code domain power equation includes a squared termthat is the absolute value of the summation over one Walsh period of thecorrelation between Z and R*. It has been recognized that more accuracycan be brought into the measurement process by increasing the summationlength inside the absolute value so that k, instead of taking on valuesfrom 1 to 64, would take on values from 1 to m, where m=64n, as follows:##EQU2##

Two problems arise when increasing the length of the summation togreater than a Walsh period, or 64 chips. Data symbols must be presentin the reference in order for the correlation to be coherent acrosssymbol boundaries. For instance, if Z contained two symbols, a 1 and a-1, but the reference contained no data, the summation over the twosymbols, if no other errors were introduced, would be zero. Anotherproblem arising from the increased summation interval is one offrequency tolerance. It is known that to make a measurement over oneWalsh period, a frequency offset of no more than around 200 Hz can betolerated. This is dictated by the amount of tolerable phase change overone measurement period, in this case, being one Walsh period. When themeasurement period is increased from one Walsh period to many Walshperiods, the maximum tolerable phase change over the measurement perioddoes not change, thereby decreasing the amount of tolerable frequencyoffset.

The present invention solves both of these problems. The summationinterval can be increased without bound, while not requiring data to bepresent in the reference waveform and also not requiring a tighterfrequency offset tolerance than that which is required for theintegration over one Walsh period, or about 200 Hz.

The present invention realizes that the equation with the increasedcorrelation time is equivalent to the following: ##EQU3## where n=m/64,the inner summation is over, and bounded by, one Walsh period, and theinner summation has the correct sign. By breaking the increasedsummation interval into multiples of symbol times as defined by theWalsh periods, the significance of the data has been removed. Inaddition, since each inner summation is only over one Walsh period, thetolerable frequency offset remains at about 200 Hz.

It is recognized that this approach is not error free. Over any onesymbol, there exists a probability that the summation over the Walshperiod will be equal to +1, -1, or any value distributed thereabout.This is shown in FIG. 8 where two exemplary probability densityfunctions (PDF) are shown. Referring now to FIG. 8, PDF 810 shows thepossible result of correlating over one Walsh period when the actualdata is equal to +1. Over most of the area contained under PDF 810, theresult of equation 2 is the same as equation 1 because the absolutevalue operation over the Walsh period will preserve the correct sign,and therefore, no error will be introduced. The area 830, however,represents an area where equation 2 would contribute an error becausethe symbol was a +1 and the absolute value operation would report theincorrect sign. Likewise, PDF 820 shows the possible result ofcorrelating over one Walsh period when the actual data is equal to -1.There is also a corresponding area 840 where an error can becontributed.

It has been found that these errors can essentially be removed by notincluding results from the inner summation of equation 2 that are closeto zero. In FIG. 8 there are shown two delta values, a positive delta850 and a negative delta 860, the range between them being termed apossible error range. The delta values 850 and 860 are defined such thatif the inner summation over a Walsh period produces a result within thearea bounded by the delta values, it is not included in the outersummation. When the delta values are defined such that the majority ofthe error areas 830 and 840 are between them, and are not included inthe larger summation of equation 2, the error is essentially removed andthe benefits of the increased summation interval are realized.

FIG. 9 shows a circuit representing the details of summer 64, which iscapable of performing the steps as outlined in the previous paragraph.This detail of summer 64 is implemented in one embodiment of theinvention, that embodiment being the one which desires to minimize theerror while increasing the measurement accuracy through a correspondingincrease in correlation length.

In FIG. 9, summer 910 performs the sum over a single Walsh period andthen performs an absolute value function. Comparator 920 compares theoutput of summer 910 with an error range provided by processor 90. Thiserror range corresponds to the region between the positive delta and thenegative delta as shown in FIG. 8. The output of summer 910 is thenconditionally included in the outer sum of summer 930. The error rangemay be defined arbitrarily small so that all absolute values from summer910 are included in the sum performed by summer 930.

The present invention, in many of its attendant advantages will beunderstood from the foregoing description and it will be apparent thatvarious changes may be made in the form, construction, and thearrangement of the parts, without departing from the spirit and scope ofthe invention, or sacrificing all of their material advantages, the formherein being merely a preferred or exemplary embodiment thereof.

Accordingly, it is intended that the appended claims cover allmodifications of the invention which fall within the true spirit andscope of the invention.

What is claimed is:
 1. An apparatus, responsive to a code divisionmultiple access (CDMA) signal for determining signal quality of the CDMAsignal, comprising:circuit means for determining a correlation functionof the CDMA signal and a reference signal over at least one Walsh codeperiod for each of a plurality of Walsh code channels, wherein saidreference signal consists solely of either +1 or -1 digital valuesthereby simplifying overall hardware and operations, wherein saidcircuit means includes:means for determining a summation of a magnitudesquared of said correlation function of the CDMA signal and saidreference signal for each Walsh code channel over at least one Walshcode period; and means for determining a summation of a magnitudesquared of the CDMA signal; and parameter determining means, responsiveto said correlation function, for determining at least one parameter ofthe CDMA signal.
 2. The apparatus of claim 1 wherein said parameterdetermining means includes means for determining a pilot timing relativeto a CDMA base station timing reference.
 3. The apparatus of claim 2wherein said means for determining said pilot timing includes:means fordetermining a first pilot channel code domain power at a positive timedistance of one half chip time from a current sample time; means fordetermining a second pilot channel code domain power at a negative timedistance of one half chip time from said current sample time; means fordetermining a difference between said first pilot channel code domainpower and said second pilot channel code domain power; in response tosaid difference, means for adjusting said current sample time; and meansfor determining said pilot timing as a difference between said currentsample time and said CDMA base station timing reference.
 4. Theapparatus of claim 1 wherein said parameter determining means includesmeans for determining a timing offset of each of said plurality of Walshcode channels relative to a pilot timing.
 5. The apparatus of claim 4wherein said means for determining said timing offset includes:means fordetermining said pilot timing; means for determining a first codechannel code domain power at a positive time distance of one half chiptime from a current sample time; means for determining a second codechannel code domain power at a negative time distance of one half chiptime from said current sample time; means for determining a differencebetween said first code channel code domain power and said second codechannel code domain power; in response to said difference, means foradjusting said current sample time; means for determining a code timingas a difference between said current sample time and a CDMA base stationtiming reference; and means for determining said timing offset as adifference between said code timing and said pilot timing.
 6. Theapparatus of claim 1 wherein said parameter determining means includesmeans for determining a phase of a pilot channel.
 7. The apparatus ofclaim 6 wherein said means for determining said phase of said pilotchannel includes:means for performing said correlation function over atleast one Walsh code period to produce a magnitude and said phase ofsaid pilot channel.
 8. The apparatus of claim 1 wherein said parameterdetermining means includes means for determining a phase offset for eachof said plurality of Walsh code channels relative to a phase of a pilotchannel.
 9. The apparatus of claim 8 wherein said means for determiningsaid phase offset includes:means for determining said phase of saidpilot channel over at least one Walsh code period; means for performingsaid correlation function over said at least one Walsh code period toproduce a Walsh code channel magnitude and a Walsh code channel phase;and means for determining said phase offset as a difference between saidWalsh code channel phase and said phase of said pilot channel.
 10. Theapparatus of claim 1 wherein said parameter determining means includesmeans for determining a frequency error of the CDMA signal bydetermining a phase difference of a Walsh code channel at two differenttimes.
 11. The apparatus of claim 10 wherein said means for determiningsaid frequency error includes:means for performing said correlationfunction at a first time over at least one Walsh code period to producea first Walsh code channel magnitude and a first Walsh code channelphase; means for performing said correlation function at a second timeover at least one Walsh code period to produce a second Walsh codechannel magnitude and a second Walsh code channel phase; and means fordetermining said frequency error as a delta phase divided by a deltatime, said delta phase being said first Walsh code channel phasesubtracted from said second Walsh code channel phase, and said deltatime being said first time subtracted from said second time.
 12. Theapparatus of claim 11 wherein said Walsh code channel is a pilotchannel.
 13. The apparatus of claim 11 wherein said Walsh code channelis a non-pilot channel.
 14. The apparatus of claim 1 wherein saidparameter determining means includes determining a code domain power forat least one of said plurality of Walsh code channels, and wherein apower value for said reference signal is a constant.
 15. The apparatusof claim 1 wherein said circuit means includes:means for buffering andrepeatedly outputting said CDMA signal an indeterminate number of timeswith a time offset, said means for buffering and replaying said CDMAsignal being responsive to a coarse timing control word.
 16. Theapparatus of claim 15 wherein said circuit means includes:means for chiptiming recovery, said means for chip timing recovery being responsive toa fine timing control word.
 17. The apparatus of claim 16 wherein saidcircuit means includes:processing means for control of said coarsetiming control word and said fine timing control word, said processingmeans being responsive to said summation of said magnitude squared ofsaid correlation function.
 18. The apparatus of claim 17 wherein saidprocessing means is also responsive to said summation of said magnitudesquared of said CDMA signal.
 19. A method for increasing accuracy ofCDMA waveform quality measurements of a CDMA waveform comprising thesteps of:providing a reference signal; determining a correlation betweensaid CDMA waveform and said reference signal, wherein said step ofdetermining a correlation is performed over a plurality of Walsh periodsto form a plurality of Walsh period correlation values, each of saidplurality of Walsh period correlation values corresponding to acorrelation over one Walsh period determining a plurality of absolutevalues of said plurality of Walsh period correlation values, whereineach of said plurality of absolute values corresponds to one of saidplurality of Walsh period correlation values; and determining a sum of aportion of said plurality of absolute values.
 20. The method of claim 19wherein said reference signal consists of binary values representingpositive 1s and negative 1s.
 21. The method of claim 19 wherein saidstep of determining a sum includes summing all of said plurality ofabsolute values.
 22. The method of claim 19 wherein said step ofdetermining a sum includes:defining an error range; and summing aportion of said plurality of absolute values that are outside said errorrange.
 23. An apparatus for increasing the measurement accuracy of CDMAwaveform quality measurements comprising:multiplying means forgenerating a correlation between a CDMA signal and a reference signal;means for determining a sum of said correlation over each of a pluralityof Walsh periods to produce a plurality of Walsh period correlationvalues; means for determining a plurality of absolute values of saidplurality of Walsh period correlation values, wherein each of saidplurality of absolute values corresponds to one of said plurality ofWalsh period correlation values; and means for determining a sum of anumber of said plurality of absolute values.
 24. The apparatus of claim23 wherein said reference signal is comprised of binary values.
 25. Theapparatus of claim 23 wherein said reference signal consists of binaryvalues.
 26. The apparatus of claim 23 wherein said multiplying meanscomprises circuit means, responsive to said reference signal, forconditional negation of said CDMA signal.
 27. The apparatus of claim 23wherein said means for determining a sum of a number of said pluralityof absolute values is comprised of:means for summing all of saidplurality of absolute values.
 28. The apparatus of claim 23 wherein saidmeans for determining a sum of a number of said plurality of absolutevalues is comprised of:means for defining an error range; and means forsumming a portion of said plurality of absolute values that are outsidesaid error range.
 29. An apparatus, responsive to a code divisionmultiple access (CDMA) signal for determining signal quality of the CDMAsignal, comprising:circuit means for determining a correlation functionof the CDMA signal and a reference signal over at least one Walsh codeperiod for each of a plurality of Walsh code channels; and parameterdetermining means, responsive to said correlation function, fordetermining at least one parameter of the CDMA signal, wherein saidparameter determining means includes means for determining a pilottiming relative to a CDMA base station timing reference, and whereinsaid means for determining said pilot timing includes:means fordetermining a first pilot channel code domain power at a positive timedistance of one half chip time from a current sample time; means fordetermining a second pilot channel code domain power at a negative timedistance of one half chip time from said current sample time; means fordetermining a difference between said first pilot channel code domainpower and said second pilot channel code domain power; in response tosaid difference, means for adjusting said current sample time; and meansfor determining said pilot timing as a difference between said currentsample time and said CDMA base station timing reference.
 30. Anapparatus, responsive to a code division multiple access (CDMA) signalfor determining signal quality of the CDMA signal, comprising:circuitmeans for determining a correlation function of the CDMA signal and areference signal over at least one Walsh code period for each of aplurality of Walsh code channels; and parameter determining means,responsive to said correlation function, for determining at least oneparameter of the CDMA signal, wherein said parameter determining meansincludes means for determining a timing offset of each of said pluralityof Walsh code channels relative to a pilot timing, and wherein saidmeans for determining said timing offset includes:means for determiningsaid pilot timing; means for determining a first code channel codedomain power at a positive time distance of one half chip time from acurrent sample time; means for determining a second code channel codedomain power at a negative time distance of one half chip time from saidcurrent sample time; means for determining a difference between saidfirst code channel code domain power and said second code channel codedomain power; in response to said difference, means for adjusting saidcurrent sample time; means for determining a code timing as a differencebetween said current sample time and a CDMA base station timingreference; and means for determining said timing offset as a differencebetween said code timing and said pilot timing.
 31. An apparatus,responsive to a code division multiple access (CDMA) signal fordetermining signal quality of the CDMA signal, comprising:circuit meansfor determining a correlation function of the CDMA signal and areference signal over at least one Walsh code period for each of aplurality of Walsh code channels; and parameter determining means,responsive to said correlation function, for determining at least oneparameter of the CDMA signal, wherein said parameter determining meansincludes means for determining a phase offset for each of said pluralityof Walsh code channels relative to a phase of a pilot channel, andwherein said means for determining said phase offset includes:means fordetermining said phase of said pilot channel over at least one Walshcode period; means for performing said correlation function over said atleast one Walsh code period to produce a Walsh code channel magnitudeand a Walsh code channel phase; and means for determining said phaseoffset as a difference between said Walsh code channel phase and saidphase of said pilot channel.
 32. An apparatus, responsive to a codedivision multiple access (CDMA) signal for determining signal quality ofthe CDMA signal, comprising:circuit means for determining a correlationfunction of the CDMA signal and a reference signal over at least oneWalsh code period for each of a plurality of Walsh code channels; andparameter determining means, responsive to said correlation function,for determining at least one parameter of the CDMA signal, wherein saidparameter determining means includes means for determining a frequencyerror of the CDMA signal by determining a phase difference of a Walshcode channel at two different times, and wherein said means fordetermining said frequency error includes:means for performing saidcorrelation function at a first time over at least one Walsh code periodto produce a first Walsh code channel magnitude and a first Walsh codechannel phase; means for performing said correlation function at asecond time over at least one Walsh code period to produce a secondWalsh code channel magnitude and a second Walsh code channel phase; andmeans for determining said frequency error as a delta phase divided by adelta time, said delta phase being said first Walsh code channel phasesubtracted from said second Walsh code channel phase, and said deltatime being said first time subtracted from said second time.
 33. Theapparatus of claim 32 wherein said Walsh code channel is a pilotchannel.
 34. The apparatus of claim 32 wherein said Walsh code channelis a non-pilot channel.
 35. An apparatus, responsive to a code divisionmultiple access (CDMA) signal for determining signal quality of the CDMAsignal, comprising:circuit means for determining a correlation functionof the CDMA signal and a reference signal over at least one Walsh codeperiod for each of a plurality of Walsh code channels; and parameterdetermining means, responsive to said correlation function, fordetermining at least one parameter of the CDMA signal; wherein saidcircuit means includes:means for determining a summation of a magnitudesquared of said correlation function of the CDMA signal and saidreference signal for each Walsh code channel over at least one Walshcode period; and means for determining a summation of a magnitudesquared of the CDMA signal.
 36. The apparatus of claim 35 wherein saidcircuit means includes:means for buffering and repeatedly outputtingsaid CDMA signal an indeterminate number of times with a time offset,said means for buffering and replaying said CDMA signal being responsiveto a coarse timing control word.
 37. The apparatus of claim 36 whereinsaid circuit means includes:means for chip timing recovery, said meansfor chip timing recovery being responsive to a fine timing control word.38. The apparatus of claim 37 wherein said circuit meansincludes:processing means for control of said coarse timing control wordand said fine timing control word, said processing means beingresponsive to said summation of said magnitude squared of saidcorrelation function.
 39. The apparatus of claim 38 wherein saidprocessing means is also responsive to said summation of said magnitudesquared of said CDMA signal.